separation by implantation of oxygen SOI waferSIMOX

基本解釋SOI 晶圓

網(wǎng)絡(luò)釋義

1)separation by implantation of oxygen SOI waferSIMOX,SOI 晶圓2)SOI wafer,SOI晶圓3)bonding silicon on insulator wafer,矽絕緣體(SOI) 接合晶圓4)SOI,SOI5)Silicon on insulator,SOI6)wafer,晶圓7)Wafer bumping,晶圓凸起8)300mm wafer line,300mm晶圓線(xiàn)9)wafer fabrication,晶圓加工10)(111)silicon,(111)硅晶圓

用法和例句

The quality of SOI wafer mainly depends on the structure of Top-Si as well as BOX(Buried Oxide).

SOI晶圓材料正在成為制備IC芯片的主要原材料。

Study of the Single-Event Effect of SOI NMOSFET by 3-D Simulation;

SOI NMOSFET單粒子效應(yīng)的3-D模擬

The Design of Three-Axis Accelerometer Based on SOI;

基于SOI的三軸壓阻微加速度計(jì)的設(shè)計(jì)

Simulation experiment of tolerance of irradiation about domestic SOI 1750A microprocessor;

國(guó)產(chǎn)SOI 1750A微處理器抗輻射效應(yīng)模擬試驗(yàn)

An ultracompact 3 dB coupler is designed and fabricated in silicon on insulator,based on 1×2 line tapered multimode interference (MMI) coupler.

采用線(xiàn)錐形結(jié)構(gòu) ,在 silicon- on- insulator(SOI)材料上設(shè)計(jì)并實(shí)現(xiàn)了一種新的緊縮型 3- d B多模干涉耦合器(MMI) 。

A 4×4 area modulation silicon on insulator (SOI) multimode interference coupler optical switch, composed of four cascaded 2×2 area modulation optical switches, has been designed.

根據(jù)區(qū)域調(diào)制多模干涉耦合器光開(kāi)關(guān)的工作原理 ,以 2× 2區(qū)域調(diào)制多模干涉光開(kāi)關(guān)為基礎(chǔ) ,采用級(jí)聯(lián)的方式設(shè)計(jì)了 4× 4區(qū)域調(diào)制多模干涉SOI光波導(dǎo)開(kāi)關(guān)。

Silicon on insulator(SOI) structure, as a very large scale integrated circuit(VLSI) wafer, has attractive features such as radiationhardening, no parasitic capacitance and latchup effect.

絕緣體上生長(zhǎng)的薄單晶硅膜 (SOI)具有良好的橫向絕緣、抗輻照、無(wú)鎖存效應(yīng)和無(wú)寄生電容 ,并能有效地提高硅集成電路的速度和集成度 ,在深亞微米 VL SI技術(shù)中 ,具有很大的優(yōu)勢(shì)和潛力。

Evolution of Wafer-Surface Preparation for Semiconductor Industry;

半導(dǎo)體產(chǎn)業(yè)中晶圓片表面處理的發(fā)展

The structural design of the wafer expansion device was put forward.

該裝置可完成片盒、內(nèi)圈和外圈的輸入和取片動(dòng)作,實(shí)現(xiàn)擴(kuò)晶過(guò)程張緊力的調(diào)節(jié)控制、分離晶圓和襯架、排出空片盒和廢棄的襯架等。

We present a FEM method for forecasting the suitable pressure on the retaining ring,which is critical in manufacturing good quality wafers.

隨著晶圓直徑的增加,在CMP加工過(guò)程中,晶圓邊緣容易出現(xiàn)"過(guò)磨(over-grinding)"現(xiàn)象,降低了平坦度和晶圓利用率。

According to the characteristics,the modeling problem using Petri net for cluster tools in wafer fabrication was studied.

晶圓加工過(guò)程中使用的模塊化組合設(shè)備具有可重構(gòu)性,設(shè)備配置的復(fù)雜程度由晶圓加工工藝方案決定,針對(duì)這一特點(diǎn),研究了晶圓加工系統(tǒng)的Petri網(wǎng)建模問(wèn)題。

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